Analysis of the impact of process variations on static logic circuits versus Fan-in

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008

Volumn , Issue , 2008, Pages 137-140

  Alioto, Massimo ^a   Palumbo, Gaetano ^b   Pennisi, Melita ^b  

^a UNIVERSITY OF SIENA   (Italy)

^b UNIVERSITY OF CATANIA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC NETWORK ANALYSIS; MONTE CARLO METHODS; NETWORKS (CIRCUITS); SWITCHING CIRCUITS; SWITCHING THEORY; TIME DELAY; TRANSISTORS;

ANALYTICAL MODELS; CIRCUIT ANALYSES; DELAY VARIATIONS; DESIGN PARAMETERS.; MONTE CARLO SIMULATIONS; PROCESS VARIATIONS; STACKED TRANSISTORS; TRANSISTOR SIZES;

LOGIC CIRCUITS;

EID: 57849088846     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICECS.2008.4674810     Document Type: Conference Paper

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