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Volumn , Issue , 2007, Pages 534-541

Cache organizations for H.264/AVC motion compensation

Author keywords

[No Author keywords available]

Indexed keywords

AND REAL TIME; CACHE LINES; CACHE ORGANIZATIONS; CONFLICT MISSES; DATA ACCESSING; DIRECT MAPPED CACHE; FRAME MEMORY; H.264/AVC; IN ORDER; INTERNATIONAL CONFERENCES; MEMORY ARCHITECTURE(MA); MEMORY BANDWIDTHS; PERFORMANCE IMPROVEMENTS; PRE-FETCHING; PRE-FETCHING SCHEMES; PREFETCH; SEQUENTIAL DATA;

EID: 46449102671     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RTCSA.2007.74     Document Type: Conference Paper
Times cited : (15)

References (10)
  • 1
    • 46449094182 scopus 로고    scopus 로고
    • Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 and ISO/EC 14496-10 AVC, May 2003.
    • Joint Video Team, Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification, ITU-T Rec. H.264 and ISO/EC 14496-10 AVC, May 2003.
  • 2
    • 33646787480 scopus 로고    scopus 로고
    • Motion compensation memory access optimization strategies for H.264/AVC decoder
    • March
    • RongGang Wang, JinTao Li, and Chao Huang, "Motion compensation memory access optimization strategies for H.264/AVC decoder," in Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing, vol. 5, pp. 97-100, March 2005.
    • (2005) Proc. IEEE Int. Conf. Acoustics, Speech, and Signal Processing , vol.5 , pp. 97-100
    • Wang, R.1    Li, J.2    Huang, C.3
  • 3
    • 46449132548 scopus 로고    scopus 로고
    • Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder
    • August
    • Chuan-Yung Tsai, Tung-Chien Chen, To-Wei Chen, and Liang-Gee Chen, "Bandwidth optimized motion compensation hardware design for H.264/AVC HDTV decoder," in Proc. Int. Symp. Circuits and Systems, vol. 2, pp. 273-276, August 2005.
    • (2005) Proc. Int. Symp. Circuits and Systems , vol.2 , pp. 273-276
    • Tsai, C.-Y.1    Chen, T.-C.2    Chen, T.-W.3    Chen, L.-G.4
  • 7
    • 67649092274 scopus 로고    scopus 로고
    • Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining for High Definition Videos
    • May
    • T. W. Chen, Y. W. Huang, T. C. Chen, Y. H. Chen, C. Y. Tsai, and L. G. Chen, "Architecture Design of H.264/AVC Decoder with Hybrid Task Pipelining for High Definition Videos," in Proc. Int. Symp. Circuits and Systems, vol. 3, pp. 2931-2934, May 2005.
    • (2005) Proc. Int. Symp. Circuits and Systems , vol.3 , pp. 2931-2934
    • Chen, T.W.1    Huang, Y.W.2    Chen, T.C.3    Chen, Y.H.4    Tsai, C.Y.5    Chen, L.G.6
  • 9
    • 0035509949 scopus 로고    scopus 로고
    • High-performance and low-power memory-interface architecture for video processing applications
    • Nov
    • Hansoo Kim and In-Cheol Park, "High-performance and low-power memory-interface architecture for video processing applications," IEEE Trans. Circuits and Systems for Video Technology, vol. 11, pp.1160-1170, Nov. 2001.
    • (2001) IEEE Trans. Circuits and Systems for Video Technology , vol.11 , pp. 1160-1170
    • Kim, H.1    Park, I.-C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.