메뉴 건너뛰기




Volumn 51, Issue 3, 2005, Pages 1006-1013

High throughput and low memory access sub-pixel interpolation architecture for H.264/AVC HDTV decoder

Author keywords

AVC; H.264 Sub pixel interpolation; HDTV

Indexed keywords

DATA STRUCTURES; DECODING; HIGH DEFINITION TELEVISION; IMAGE ANALYSIS; IMAGE CODING; IMAGE COMMUNICATION SYSTEMS; IMAGE COMPRESSION; IMAGE QUALITY; INTERPOLATION; MOTION COMPENSATION; SIGNAL FILTERING AND PREDICTION;

EID: 27144481545     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2005.1510515     Document Type: Article
Times cited : (43)

References (11)
  • 1
    • 0042096160 scopus 로고    scopus 로고
    • "Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC"
    • Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVTG050
    • Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, "Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC", JVTG050, 2003.
    • (2003)
  • 4
    • 0035509949 scopus 로고    scopus 로고
    • "High-Performance and Low-Power Memory-Interface Archeticture for Video Processing Application"
    • Nov
    • Hansoo Kim and In-Cheol Park, "High-Performance and Low-Power Memory-Interface Archeticture for Video Processing Application", IEEE Tran. Circuits Syst. Video Tech., vol 11, pp1160-1170, Nov.2001
    • (2001) IEEE Tran. Circuits Syst. Video Tech. , vol.11 , pp. 1160-1170
    • Kim, H.1    Park, I.-C.2
  • 5
    • 0029194177 scopus 로고
    • "Architecture and Memory Requirements for stand-alone and hierarchical MPEG-HDTV-Decoders with Synchronous DRAMs"
    • May
    • Marco Winzker, Peter Pirsch and Jochen Reimers, "Architecture and Memory Requirements for stand-alone and hierarchical MPEG-HDTV-Decoders with Synchronous DRAMs", ISCAS'95, IEEE Inter.Sym., pp609-612,May 1995
    • (1995) ISCAS'95, IEEE Inter.Sym. , pp. 609-612
    • Winzker, M.1    Pirsch, P.2    Reimers, J.3
  • 6
    • 0037481109 scopus 로고    scopus 로고
    • "Efficient Memory IP Design for HDTV Coding Applications"
    • June
    • Shih-Chang Hsia, "Efficient Memory IP Design for HDTV Coding Applications", IEEE Trans. Circuits Syst. Video Tech. vol 13, pp465-471, June 2003
    • (2003) IEEE Trans. Circuits Syst. Video Tech. , vol.13 , pp. 465-471
    • Hsia, S.-C.1
  • 7
    • 6344251986 scopus 로고    scopus 로고
    • "Model for estimating prediction bandwidth for H.26L"
    • JVT-E093
    • Adrian Wise, Rob Whitton and Yazid, "Model for estimating prediction bandwidth for H.26L", JVT-E093, 2002
    • (2002)
    • Wise, A.1    Whitton, R.2    Yazid3
  • 10
    • 21644476517 scopus 로고    scopus 로고
    • " High performance synchronous DRAMs controller in H.264 HDTV decoder"
    • Proceedings. 7th International Conference on Volume 3, 18-21 Oct
    • Jiahui Zhu, Ligang Hou, Wuchen Wu, Ronggang Wang, Chao Huang, JinTao Li, " High performance synchronous DRAMs controller in H.264 HDTV decoder", Solid-State and Integrated Circuits Technology, 2004. Proceedings. 7th International Conference on Volume 3, 18-21 Oct. 2004 Page(s):1621 - 1624 vol.3
    • (2004) Solid-State and Integrated Circuits Technology, 2004. , vol.3 , pp. 1621-1624
    • Zhu, J.1    Hou, L.2    Wu, W.3    Wang, R.4    Huang, C.5    Li, J.T.6
  • 11
    • 0026392610 scopus 로고
    • "VLSI architecture and implementation of a high-speed entropy decoder"
    • 11-14 June
    • M.T. Sun, "VLSI architecture and implementation of a high-speed entropy decoder", IEEE International Sympoisum on Circuits and Systems, 1991. 11-14 June 1991 Page(s):200 - 203 vol.1
    • (1991) IEEE International Sympoisum on Circuits and Systems, 1991 , vol.1 , pp. 200-203
    • Sun, M.T.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.