Memory cache based motion compensation architecture for HDTV H.264/AVC decoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2007, Pages 2906-2909

  Yu, Li ^a   Yanmei, Qu ^a   Yun, He ^a  

^a TSINGHUA UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DECODING; INTERPOLATION; MOTION COMPENSATION; OPTIMIZATION; PIXELS; REAL TIME CONTROL;

INTERPOLATION CYCLES; MEMORY BANDWIDTH; MEMORY CACHE;

HIGH DEFINITION TELEVISION;

EID: 34548844763     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, "Draft ITU-T recommendation, and final draft international standard of joint video specification (ITU-T Rec. H.264/ISO/IEC 14 496-10 AVC", JVTG050, 2003.
2. Ronggang Wang, Mo Li, Jintao Li, Yongdong Zhang, "High. throughput and low memory access sub-pixel interpolation, architecture for H.264/AVC HDTV decoder," IEEE Trans. Consumer Electron., vol 51, Issue3,pp. 1006-1013, Aug. 2005.
3. Chuan-Yung Tsai, Tung-Chien Chen, To-Wei Chen, Liang-Gee Chen, "Bandwidth, optimized motion, compensation hardware design for H.264/AVC HDTV decoder," Circuits and Systems on 48th. Midwest Symposium, Vol. 2, pp. 1199-1202, 7-10 Aug, 2005
4. S. Z. Wang, T. A. Lin, T. M. Liu, and C. Y. Lee, "A new motion compensation design for H.264/AVC decoder," in. Proc. of Int. Symposium on Circuits and Systems (ISCAS'05), pp. 4558-61, 2005.
5. Yu Li, Yun He, "A Highly parallel Cost-effective VLSI Implementation, for 8×8 Transform in. H.264/AVC," Proceedings of PCS2006, Beijing, April, 2006.