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Volumn , Issue , 2009, Pages 773-778

Adaptive prefetching for shared cache based chip multiprocessors

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CACHE MEMORY;

EID: 70350077814     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2009.5090768     Document Type: Conference Paper
Times cited : (7)

References (30)
  • 6
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    • An integrated hardware/software data prefetching scheme for shared-memory multiprocessors
    • E. H. Gornish and A. Veidenbaum. An integrated hardware/software data prefetching scheme for shared-memory multiprocessors. International Journal of Parallel Programming, 27(1):35-70, 1999.
    • (1999) International Journal of Parallel Programming , vol.27 , Issue.1 , pp. 35-70
    • Gornish, E.H.1    Veidenbaum, A.2
  • 8
    • 0032630821 scopus 로고    scopus 로고
    • Ultrasparc-iii: Designing third-generation 64-bit performance
    • T. Horel and G. Lauterbach. Ultrasparc-iii: Designing third-generation 64-bit performance. IEEE Micro, 19(3):73-85, 1999.
    • (1999) IEEE Micro , vol.19 , Issue.3 , pp. 73-85
    • Horel, T.1    Lauterbach, G.2
  • 12
    • 20344374162 scopus 로고    scopus 로고
    • Niagara: A 32-way multithreaded SPARC processor
    • P. Kongetira, K. Aingaran, and K. Olukotun. Niagara: A 32-way multithreaded SPARC processor. IEEE Micro, 25(2):21-29, 2005.
    • (2005) IEEE Micro , vol.25 , Issue.2 , pp. 21-29
    • Kongetira, P.1    Aingaran, K.2    Olukotun, K.3
  • 15
    • 0034839064 scopus 로고    scopus 로고
    • Tolerating memory latency through software-controlled pre- execution in simultaneous multithreading processors
    • C.-K. Luk. Tolerating memory latency through software-controlled pre- execution in simultaneous multithreading processors. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 40-51, 2001.
    • (2001) Proceedings of the 28th Annual International Symposium on Computer Architecture , pp. 40-51
    • Luk, C.-K.1
  • 17
    • 0042366306 scopus 로고    scopus 로고
    • Architectural and compiler support for effective instruction prefetching: A cooperative approach
    • C.-K. Luk and T. C. Mowry. Architectural and compiler support for effective instruction prefetching: a cooperative approach. ACM Transactions on Computer Systems, 19(1):71-109, 2001.
    • (2001) ACM Transactions on Computer Systems , vol.19 , Issue.1 , pp. 71-109
    • Luk, C.-K.1    Mowry, T.C.2
  • 19
    • 0031988272 scopus 로고    scopus 로고
    • Tolerating latency in multiprocessors through compiler-inserted prefetching
    • T. C. Mowry. Tolerating latency in multiprocessors through compiler-inserted prefetching. ACM Transactions on Computer Systems, 16(1):55-92, 1998.
    • (1998) ACM Transactions on Computer Systems , vol.16 , Issue.1 , pp. 55-92
    • Mowry, T.C.1
  • 23
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    • Cache memories
    • A. J. Smith. Cache memories. ACM Comput. Surv., 14(3):473-530, 1982.
    • (1982) ACM Comput. Surv , vol.14 , Issue.3 , pp. 473-530
    • Smith, A.J.1
  • 27
    • 0001589803 scopus 로고    scopus 로고
    • Data prefetch mechanisms
    • S. P. Vanderwiel and D. J. Lilja. Data prefetch mechanisms. ACM Comput. Surv., 32(2):174-199, 2000.
    • (2000) ACM Comput. Surv , vol.32 , Issue.2 , pp. 174-199
    • Vanderwiel, S.P.1    Lilja, D.J.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.