TEPS: Transient error protection utilizing sub-word parallelism

Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2009

Volumn , Issue , 2009, Pages 286-291

  Hong, Seokin ^a   Kim, Soontae ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP AREAS; COMBINATIONAL LOGIC; DENSE INTEGRATION; EXECUTION UNITS; SHIFT OPERATIONS; SUB-WORD PARALLELISM; TECHNOLOGY SCALING; TRANSIENT ERRORS;

EMBEDDED SYSTEMS;

EID: 70349481927     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2009.21     Document Type: Conference Paper

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