An efficient verification of quantum circuits under a practical restriction

Proceedings - 2008 IEEE 8th International Conference on Computer and Information Technology, CIT 2008

Volumn , Issue , 2008, Pages 873-879

  Yamashita, Shigeru ^a   Minato, Shin Ichi ^b   Michael Miller, D ^c  

^a NARA INSTITUTE OF SCIENCE AND TECHNOLOGY   (Japan)

^b HOKKAIDO UNIVERSITY   (Japan)

^c UNIVERSITY OF VICTORIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DECISION DIAGRAMS; INTERNATIONAL CONFERENCES; LOGIC SYNTHESIS; MATRIX FUNCTIONS; QUANTUM CIRCUIT DESIGN; QUANTUM CIRCUITS; QUANTUM COMPUTATIONS; QUANTUM FUNCTIONS; VERIFICATION METHODS; VERIFICATION SCHEME; VERIFICATION TECHNIQUES;

COMPUTATIONAL LINGUISTICS; FUNCTION EVALUATION; GRAPHIC METHODS; INFORMATION TECHNOLOGY; INTEGRATED CIRCUIT MANUFACTURE; LOGIC CIRCUITS; MATRIX ALGEBRA; NETWORKS (CIRCUITS); QUANTUM COMPUTERS; TECHNOLOGY;

QUANTUM EFFICIENCY;

EID: 51849115119     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CIT.2008.4594789     Document Type: Conference Paper

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