CAD Techniques for Power Optimization in Virtex-5 FPGAS

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 85-88

  Gupta, Subodh ^a   Anderson, Jason ^a   Farragher, Linda ^a   Wang, Qiang ^a  

^a XILINX INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; POWER MANAGEMENT;

BOARD-LEVEL; CAD TECHNIQUES; DYNAMIC POWER DISSIPATION; DYNAMIC POWER REDUCTION; POWER CONSUMED; POWER OPTIMIZATION; POWER-AWARE; VIRTEX-5;

COMPUTER AIDED LOGIC DESIGN;

EID: 84938578220     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405687     Document Type: Conference Paper

References (11)

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