Photolithography control in wafer fabrication based on process capability indices with multiple characteristics

IEEE Transactions on Semiconductor Manufacturing

Volumn 22, Issue 3, 2009, Pages 351-356

  Pearn, W L ^a   Kang, H Y ^b   Lee, A H I ^c   Liao, M Y ^d  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL CHIN YI UNIVERSITY OF TECHNOLOGY   (Taiwan)

^c CHUNG HUA UNIVERSITY   (Taiwan)

^d YUANPEI UNIVERSITY   (Taiwan)

Author keywords

Alignment accuracy; Critical dimension; Critical value; Photolithography; Photoresist thickness; Process yield

Indexed keywords

ALIGNMENT ACCURACY; COMMON CRITERIA; COMPLEX OPERATIONS; CRITICAL DIMENSION; CRITICAL VALUE; EXTENSIVE SIMULATIONS; HYPOTHESIS TESTING; MANUFACTURING INDUSTRIES; MULTIPLE CHARACTERISTICS; PERFORMANCE OF DEVICES; PERFORMANCE REQUIREMENTS; PHOTOLITHOGRAPHY PROCESS; PROCESS CAPABILITY INDICES; PROCESS PERFORMANCE; PROCESS YIELD; RELIABLE DECISION; SEMICONDUCTOR MANUFACTURING; STANDARD SIMULATION TECHNIQUES; TESTING PROCESS; WAFER FABRICATIONS; WAFER MANUFACTURING;

ALIGNMENT; PHOTORESISTORS; PROCESS CONTROL; PRODUCTION CONTROL; SILICON WAFERS; SURFACE TREATMENT;

PHOTOLITHOGRAPHY;

EID: 70349306107     PISSN: 08946507     EISSN: None     Source Type: Journal    
DOI: 10.1109/TSM.2009.2024851     Document Type: Article

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