A modular all-digital PLL architecture enabling both 1-to-2GHz and 24-to-32GHz operation in 65NM CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 516-518

  Rylyakov, A V ^a   Tierno, J A ^a   Turker, D Z ^b   Plouchart, J O ^a   Ainspan, H A ^a   Friedman, D ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b TEXAS A AND M UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MODULATORS;

ALL-DIGITAL PLL; CIRCUIT CONTROL; DELTA SIGMA MODULATOR; DIGITAL PLL; FRACTIONAL-N SYNTHESIZER; FREQUENCY RANGES; LOOP FILTER; PERIOD JITTER;

PHASE LOCKED LOOPS;

EID: 49549102226     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523284     Document Type: Conference Paper

References (5)

1. R. B. Staszewski, J. L. Wallberg, S. Rezeq, et al., "All-Digital PLL and Transmitter for Mobile Phones" IEEE J. Solid State Circuits, vol. 40, no. 12, pp. 2469-2482, Dec 2005.
2. V. Kratyuk, P. Hanumolu, K. Ok, et al., "A digital PLL with a stochastic time-to-digital converter" Dig. Symp. VLSI Circuits, pp. 38-39, Jun. 2006.
3. A. V. Rylyakov, J. A. Tierno, G. J. English, et al., "A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS ADPLL in 65nm SOI", ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2007.
4. J. A. Tierno, A. V. Rylyakov, D. Friedman, "A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI", accepted for publication in IEEE J. Solid-State Circuits, Jan. 2008.
5. A. Hajimiri, S. Limotyrakis, and T H. Lee, "Jitter and Phase Noise in Ring Oscillators", IEEE J. Solid -State Circuits, vol. 34, no. 6, pp. 790-804, Jun. 1999.