Digitally-Enhanced Phase-Locking Circuits

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007

Volumn , Issue , 2007, Pages 361-368

  Hanumolu, Pavan Kumar ^a   Wei, Gu Yeon ^a,b   Moon, Un Ku ^a   Mayaram, Kartikeya ^a  

^a Oregon State University   (United States)

^b HARVARD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; FREQUENCY CONVERTERS; INTEGRATED CIRCUITS;

BUILDING BLOCKES; DEEP SUBMICRON CMOS; DIGITAL SYSTEM; DIGITAL TECHNIQUES; DIGITALLY CONTROLLED OSCILLATORS; MEASURED RESULTS; PHASE ACCUMULATORS; TIME TO DIGITAL CONVERTERS;

LOCKS (FASTENERS);

EID: 70349295848     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CICC.2007.4405753     Document Type: Conference Paper

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