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Volumn 30, Issue 9, 2009, Pages 999-1001

Low-threshold-voltage TaN/LaTiO n-MOSFETs with small EOT

Author keywords

LaTiO; Low Vt; Solid phase diffusion (SPD)

Indexed keywords

EQUIVALENT OXIDE THICKNESS; INTERFACIAL REACTIONS; LATIO; LOW THRESHOLD VOLTAGE; LOW THRESHOLDS; LOW VT; NMOSFETS; SELF-ALIGNED GATE; SOLID-PHASE DIFFUSION; SOLID-PHASE DIFFUSION (SPD);

EID: 70049102515     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2027723     Document Type: Article
Times cited : (11)

References (15)
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    • 50249185641 scopus 로고    scopus 로고
    • K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging, in IEDM Tech. Dig, 2007, pp. 247-250
    • K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier, M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani, R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner, D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee, H. Liu, J. Maiz, B. McIntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Parsons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford, L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas, T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki, "A 45 nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193 nm dry patterning, and 100% Pb-free packaging," in IEDM Tech. Dig., 2007, pp. 247-250.
  • 13
    • 58149488746 scopus 로고    scopus 로고
    • tTaN/HfLaO n-MOSFETs using low temperature formed source-drain junctions
    • Jan
    • tTaN/HfLaO n-MOSFETs using low temperature formed source-drain junctions," IEEE Electron Device Lett., vol. 30, no. 1, pp. 75-77, Jan. 2009.
    • (2009) IEEE Electron Device Lett , vol.30 , Issue.1 , pp. 75-77
    • Lin, S.H.1    Liu, S.L.2    Yeh, F.S.3    Chin, A.4
  • 14
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    • Online, Available
    • International Technology Roadmap for Semiconductors, Process Integration, Devices, and Structures Chapter, p. 11. [Online]. Available: Www.itrs.net/Links/2007ITRS/2007_Chapters/2007_PIDS.pdf
    • Process Integration, Devices, and Structures Chapter , pp. 11


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.