SET emulation considering electrical masking effects

IEEE Transactions on Nuclear Science

Volumn 56, Issue 4, 2009, Pages 2021-2025

  Entrena, Luis ^a   Valderas, Mario García ^a   Cardenal, Raúl Fernández ^a   Garcia, Marta Portela ^a   Ongil, Celia López ^a  

^a UNIVERSIDAD CARLOS III DE MADRID   (Spain)

Author keywords

Electrical masking; Fault injection; FPGA emulation; Single event transient (SET)

Indexed keywords

ANALOG SIMULATIONS; CIRCUIT DELAYS; ELECTRICAL MASKING; FAULT INJECTION; FPGA EMULATION; LOGIC SIMULATIONS; MASKING EFFECT; NEW APPROACHES; SINGLE EVENT TRANSIENT (SET); SINGLE EVENT TRANSIENTS; THREE ORDERS OF MAGNITUDE;

ELECTRIC POTENTIAL; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); SOFTWARE TESTING;

TRANSIENTS;

EID: 69549098347     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2009.2013346     Document Type: Conference Paper

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