A new methodology for short circuit localization on integrated circuits using magnetic microscopy technique coupled with simulations

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn , Issue , 2009, Pages 208-212

  Infante, F ^a   Perdu, P ^a   Petremont, S ^b   Lewis, D ^c  

^a CNES   (France)

^b STMICROELECTRONICS   (France)

^c UNIVERSITÉ BORDEAUX 1   (France)

Author keywords

[No Author keywords available]

Indexed keywords

FAULT LOCALIZATION; MAGNETIC MEASUREMENTS; MAGNETIC MICROSCOPY; MAGNETIC SIMULATION; MAGNETIC TECHNIQUES; SHORT CIRCUIT;

ELECTRIC NETWORK ANALYSIS; FAILURE ANALYSIS; INTEGRATED CIRCUITS; QUALITY ASSURANCE; SAFETY FACTOR;

COUPLED CIRCUITS;

EID: 69249238750     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2009.5232668     Document Type: Conference Paper

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