Bit-serial single flux quantum microprocessor CORE

IEICE Transactions on Electronics

Volumn E91-C, Issue 3, 2008, Pages 342-349

  Fujimaki, Akira ^a   Tanaka, Masamitsu ^a   Yamada, Takahiro ^a   Yamanashi, Yuki ^b   Park, Heejoung ^b   Yoshikawa, Nobuyuki ^b  

^a NAGOYA UNIVERSITY   (Japan)

^b YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Bitserial; ISI; Superconductor nsicroprocessor single flux quantum

Indexed keywords

COMPUTER CIRCUITS; CROSSBAR EQUIPMENT;

BIT-SERIAL; CIRCUIT ARCHITECTURES; CIRCUIT COMPLEXITY; GENERAL-PURPOSE COMPUTING; MICRO ARCHITECTURES; MICROPROCESSOR CORE; PROCESSOR PERFORMANCE; SINGLE FLUX QUANTUM;

COMPUTER ARCHITECTURE;

EID: 68749121551     PISSN: 09168524     EISSN: 17451353     Source Type: Journal    
DOI: 10.1093/ietele/e91-c.3.342     Document Type: Article

References (23)

1. K. Nakajima, Y. Onodera, and Y. Ogawa, "Logic design of Josephson network, "J. Appl. Phys., vol.47, no.4, pp. 1620-1627, April 1976.
2. K.K. Likhazev and V.K. Semenov, "RSFQ logic/memory family: Anew Josephson-junction technology for sub-terahertz-clockfrequency digital systems, "IEEE Trans. Appl. Supercond., vol.1, no.1, pp. 3-28, March 1991.
3. W. Chen, A.V. Rylyakov, V. Patel, J.E. Lukens, and K.K. Likharev, "Superconductor digital frequency divider operating up to 750GHz, "Appl. Phys. Lett., vol.73, no.19, pp. 2817-2819, Nov. 1998.
4. H. Akaike, T. Yamada, A. Fujimaki, S. Nagasawa, K. Hinode, T. Satoh, Y. Kitagawa, and M. Hidaka, "Demonstration of a 120GHz single-flux-quanhim shift register circuit based on a 10kA/cm2 Nb process, "Supercond. Sci. Technol., vol.19, no.5, pp. S320-S324, May 2006.
5. M. Dorojevets, P. Bunyk, and D. Zinoviev, "FLUX chip design of 20-GHz 16-bit ulhapipelined RSFQ processor prototype based on 1.75-mm LTS technology, "IEEE Trans. Appl. Supercond., vol.11, no.1, pp. 326-332, March 2001.
6. T. Sterling, "A hybrid technology multithreaded architecture for petaflops computing, "Presented at CACR. [Online]. Available: http://htmtcacr.caltech.edu/Overview.html
7. A. Fujimaki, Y. Takai, and N. Yoshikawa, "High-end server based on complexity-reduced architecture for superconductor technology, "IEICE Trans. Electron., vol.E85-C, no.3, pp. 612-616, March 2002.
8. Q. Liu, T. Van Duzer, X. Meng, S.R. Whiteley, K. Fujiwara, T. Tomida, K. Tokuda, and N. Yoshikawa, "Simulation and measurements on a 64-kbit hybrid Josephson-CMOS memory, "IEEE. Trans. Appl. Supercond., vol.15, no.2, pp. 415-418, June 2005.
9. Y. Hashimoto, S. Yorozu, T. Satoh, and T. Miyazaki, "Demonstration of chip-to-chip transmission of single-flux-quantum pulse at throughputs beyond 100 Gbps, "Appl. Phys. Lett., vol.87, 022502, 2005.
10. S. Nagasawa, Y. Hashimoto, H. Numata, and S. Tahara, "A 380ps, 9.5mW Josephson 4-Kbit RAM operated at a high bit yield, "IEEE Trans. Appl. Supercond., vol.5, no.2, pp. 2447-2452, Jan. 1995.
11. S. Yorozu, Y. Kameda, H. Terai, A. Fujimaki, T. Yamada, and S. Tahara, "A single flux quantum standard logic cell library, "Physica C, vol.378-381, pp. 1471-1474, Sept. 2002.
12. Improved version of the program written in the following article, N. Mori, A. Akahori, T. Sato, N. Takeuchi, A. Fujimaki, and H. Hayakawa, "A new optimization procedure for single flux quantum circuits, "Physica C, vol.357-360, pp. 1557-1560, 2001.
13. V.K. Semenov (private communication).
14. N.A. Joukov, M.S. Tivari, and V.K. Semenov, "RSFQ signed serial multiplier-accumulator, "IEEE Trans. Appl. Supercond., vol.15, no.1, pp. 49-53, March 2005.
15. Y. Hashimoto, S. Yorozu, Y. Kameda, and V.K. Semenov, "A design approach to passive interconnects for single flux quantum logic cells, "IEEE Trans. Appl. Supercond., vol.13, no.2, pp. 535-538, June 2003.
16. T. Yamada, H. Ryoki, A. Fujimaki, and S. Yorozu, "Flexible superconducting passive interconnects with 50-Gb/s signal transmissions in single-flux-quantum circuits, "Jpn. J. Appl. Phys., vol.45, no. 2A, pp. 752-757, 2006.
17. T. Yamada and A. Fujimaki, "A novel splitter with four fan-outs for ballistic signal distribution in single-flux-quantum circuits up to 50Gb/s, "Jpn. J. Appl. Phys., vol.45, no.9, pp. L262-L264, 2006.
18. J.L. Hennessy and D.A. Patterson, Computer Architecture: A Quantitative Approach, 2nd ed., Morgan Kaufmann, San Francisco, CA, 1990.
19. M. Tanaka, T. Kondo, T. Kawamoto, Y. Kamiya, K. Fujiwaza, Y. Yamanashi, A. Akimoto, A. Fujimaki, N. Yoshikawa, H. Terai, and S. Yorozu, "Design of a data path for single-flux-quantum microprocessors with multiple ALUs, "Physica C, vol.426-431, pp. 1693- 1698, Nov. 2005.
20. M. Tanaka, T. Kawamoto, Y. Yamanashi, Y. Kamiya, A. Akimoto, K. Fujiwaza, A. Fujimaki, N. Yoshikawa, H. Terai, and S. Yorozu, "Design of a pipelined 8-bit-serial single-flux-quantum microprocessors with multiple ALUs, "Supercond. Sci. Technol., vol.19, no.5, pp. S344-S349, May 2006.
21. Y. Yamanashi, A. Akimoto, N. Yoshikawa, M. Tanaka, T. Kawamoto, Y. Kamiya, A. Fujimaki, H. Terai, and S. Yorozu, "A new design approach for control circuits of pipeline single-fluxquantum microprocessors, "Supercond. Sci. Technol., vol.19, no.5, pp. S340-S343, May 2006.
22. N. Irie, M. Tanaka, Y. Yamanashi, H.-J. Pink, N. Yoshikawa, H. Terai, S. Yorozu, and A. Fujimaki, "Scalable cache memory for a bitserial single-flux-quantum microprocessor, "Extend. Abst. of 11th Int. Supercond. Electronics Conf. (ISEC2007), Wasihngton D.C., U.S.A. June 2007.
23. Y. Yamanashi, T. Nishigai, and N. Yoshikawa, "Study of LR-loading technique for low-power single-flux-quantum circuits, "IEEE Trans. Appl. Supercond., vol.17, no.2, pp. 150-153, June 2007.