Simulation and measurements on a 64-kbit hybrid josephson-CMOS memory

IEEE Transactions on Applied Superconductivity

Volumn 15, Issue 2 PART I, 2005, Pages 415-418

  Liu, Q ^a   Van Duzer, T ^a   Meng, X ^a   Whiteley, S R ^a   Fujiwara, K ^b   Tomida, T ^b   Tokuda, K ^b   Yoshikawa, N ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b YOKOHAMA NATIONAL UNIVERSITY   (Japan)

Author keywords

Access time; Hybrid memory; Interface circuit; Low temperature CMOS

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DATA ACQUISITION; HYBRID INTEGRATED CIRCUITS; LEAKAGE CURRENTS; MOSFET DEVICES; OSCILLATORS (ELECTRONIC); RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

ACCESS TIME; HYBRID MEMORY; INTERFACE CIRCUITS; LOW TEMPERATURE CMOS;

JOSEPHSON JUNCTION DEVICES;

EID: 22044446224     PISSN: 10518223     EISSN: None     Source Type: Journal    
DOI: 10.1109/TASC.2005.849863     Document Type: Conference Paper

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