Maze routing steiner trees with delay versus wire length tradeoff

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 8, 2009, Pages 1073-1086

  Hentschke, Renato ^a,c   Narasimhan, Jaganathan ^b   Johann, Marcelo ^a   Reis, Ricardo ^a  

^a FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Delay; Maze search; Routing; Steiner trees

Indexed keywords

BIASING TECHNIQUES; DELAY; DELAY OPTIMIZATION; MAZE ROUTING; MAZE SEARCH; OPTIMAL TOPOLOGIES; PATH LENGTH; PATH SEARCH; RECTILINEAR STEINER TREES; ROUTING; STATE OF THE ART; STEINER TREES; WIRE LENGTH;

LEARNING ALGORITHMS; TOPOLOGY; WIRE;

ROUTING ALGORITHMS;

EID: 68549092567     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2019798     Document Type: Article

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