Relaxing conflict between read stability and writability in 6T SRAM cell using asymmetric transistors

IEEE Electron Device Letters

Volumn 30, Issue 8, 2009, Pages 852-854

  Kim, Jae Joon ^a   Bansal, Aditya ^a   Rao, Rahul ^a   Lo, Shih Hsien ^a   Chuang, Ching Te ^a,b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

Asymmetric MOSFET; Read stability; SRAM; Writability

Indexed keywords

6T-SRAM; ASYMMETRIC MOSFET; MOS-FET; READ STABILITY; SOURCE CHARACTERISTICS; SRAM; SRAM CELL; WRITABILITY; WRITE OPERATIONS;

CELL MEMBRANES; MOSFET DEVICES; STATIC RANDOM ACCESS STORAGE;

STABILITY;

EID: 68249152533     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2024014     Document Type: Article

References (11)

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