-
1
-
-
17044420157
-
New approaches to total power reduction including runtime leakage
-
March 01
-
D. Sylvester, "New approaches to total power reduction including runtime leakage," University of Texas VLSI Seminar Series, March 01, 2004.
-
(2004)
University of Texas VLSI Seminar Series
-
-
Sylvester, D.1
-
2
-
-
4544305546
-
A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
-
pp., December
-
T. Ghani, et. al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," IEDM Tech Dig, pp., December 2003.
-
(2003)
IEDM Tech Dig
-
-
Ghani, T.1
-
3
-
-
13244250931
-
Scalability of strained silicon CMOSFET and high drive current enhancement in the 40nm gate length technology
-
pp., December
-
T. Sanuki, et. al., "Scalability of strained silicon CMOSFET and high drive current enhancement in the 40nm gate length technology," IEDM Tech Dig, pp., December 2003.
-
(2003)
IEDM Tech Dig
-
-
Sanuki, T.1
-
4
-
-
0036927652
-
Strained silicon MOSFET technology
-
pp., December
-
J. Hoyt, H. Nayfeh, S. Eguchi, I. Aberg, G. Xia, T. Drake, E. Fitzgerald, and D. Antoniadis, "Strained silicon MOSFET technology," IEDM Tech Dig, pp., December 2002.
-
(2002)
IEDM Tech Dig
-
-
Hoyt, J.1
Nayfeh, H.2
Eguchi, S.3
Aberg, I.4
Xia, G.5
Drake, T.6
Fitzgerald, E.7
Antoniadis, D.8
-
5
-
-
0036932194
-
High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric
-
pp., December
-
H. Shang, et. al., "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," IEDM Tech Dig, pp., December 2002.
-
(2002)
IEDM Tech Dig
-
-
Shang, H.1
-
6
-
-
0036923998
-
A sub-400C germanium MOSFET technology with high-k dielectric and metal gate
-
pp., December
-
C. Chui, H. Kim, D. Chi, B. Triplett, P. McIntyre, and K. Saraswat, "A sub-400C germanium MOSFET technology with high-k dielectric and metal gate," IEDM Tech Dig, pp., December 2002.
-
(2002)
IEDM Tech Dig
-
-
Chui, C.1
Kim, H.2
Chi, D.3
Triplett, B.4
McIntyre, P.5
Saraswat, K.6
-
7
-
-
0036927657
-
TinFET process refinements for improved mobility and gate work function engineering
-
pp., December
-
Y. Choi, L. Chang, P. Rnade, J. Lee, D. Ha, S. Balasubramanian, A. Agarwal, M. Ameen, T. King, and J. Bokor, 'TinFET process refinements for improved mobility and gate work function engineering," IEDM Tech Dig, pp., December 2002.
-
(2002)
IEDM Tech Dig
-
-
Choi, Y.1
Chang, L.2
Rnade, P.3
Lee, J.4
Ha, D.5
Balasubramanian, S.6
Agarwal, A.7
Ameen, M.8
King, T.9
Bokor, J.10
-
8
-
-
0035714801
-
FD/DG-SOI MOSFET - A viable approach to overcoming the device scaling limit
-
pp., December
-
D. Hisamoto, 'FD/DG-SOI MOSFET - a viable approach to overcoming the device scaling limit," IEDM Tech Dig, pp., December 2001.
-
(2001)
IEDM Tech Dig
-
-
Hisamoto, D.1
-
9
-
-
0036712445
-
High-performance logic and high-gain analog CMOS transistors formed by shadow-mask technique with a single implant step
-
September
-
T. Hook, J. Brown, M. Breitwisch, D. Hoyniak, and R. Mann, "High-performance logic and high-gain analog CMOS transistors formed by shadow-mask technique with a single implant step, " IEEE Trans Elec. Dev., vol. 49, pp. 1623-1627, September 2002.
-
(2002)
IEEE Trans Elec. Dev.
, vol.49
, pp. 1623-1627
-
-
Hook, T.1
Brown, J.2
Breitwisch, M.3
Hoyniak, D.4
Mann, R.5
-
12
-
-
0003514380
-
-
Cambridge, United Kingdom, Cambridge University Press
-
Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge, United Kingdom, Cambridge University Press, 1998, p300.
-
(1998)
Fundamentals of Modern VLSI Devices
, pp. 300
-
-
Taur, Y.1
Ning, T.2
|