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Volumn , Issue , 2004, Pages 229-232

Opportunities and challenges in asymmetric device implementation

Author keywords

[No Author keywords available]

Indexed keywords

CARRIER MOBILITY; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; GATES (TRANSISTOR); MICROPROCESSOR CHIPS; SEMICONDUCTOR DOPING; THRESHOLD VOLTAGE;

EID: 17044390795     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (5)

References (13)
  • 1
    • 17044420157 scopus 로고    scopus 로고
    • New approaches to total power reduction including runtime leakage
    • March 01
    • D. Sylvester, "New approaches to total power reduction including runtime leakage," University of Texas VLSI Seminar Series, March 01, 2004.
    • (2004) University of Texas VLSI Seminar Series
    • Sylvester, D.1
  • 2
    • 4544305546 scopus 로고    scopus 로고
    • A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors
    • pp., December
    • T. Ghani, et. al., "A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors," IEDM Tech Dig, pp., December 2003.
    • (2003) IEDM Tech Dig
    • Ghani, T.1
  • 3
    • 13244250931 scopus 로고    scopus 로고
    • Scalability of strained silicon CMOSFET and high drive current enhancement in the 40nm gate length technology
    • pp., December
    • T. Sanuki, et. al., "Scalability of strained silicon CMOSFET and high drive current enhancement in the 40nm gate length technology," IEDM Tech Dig, pp., December 2003.
    • (2003) IEDM Tech Dig
    • Sanuki, T.1
  • 5
    • 0036932194 scopus 로고    scopus 로고
    • High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric
    • pp., December
    • H. Shang, et. al., "High mobility p-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric," IEDM Tech Dig, pp., December 2002.
    • (2002) IEDM Tech Dig
    • Shang, H.1
  • 6
    • 0036923998 scopus 로고    scopus 로고
    • A sub-400C germanium MOSFET technology with high-k dielectric and metal gate
    • pp., December
    • C. Chui, H. Kim, D. Chi, B. Triplett, P. McIntyre, and K. Saraswat, "A sub-400C germanium MOSFET technology with high-k dielectric and metal gate," IEDM Tech Dig, pp., December 2002.
    • (2002) IEDM Tech Dig
    • Chui, C.1    Kim, H.2    Chi, D.3    Triplett, B.4    McIntyre, P.5    Saraswat, K.6
  • 8
    • 0035714801 scopus 로고    scopus 로고
    • FD/DG-SOI MOSFET - A viable approach to overcoming the device scaling limit
    • pp., December
    • D. Hisamoto, 'FD/DG-SOI MOSFET - a viable approach to overcoming the device scaling limit," IEDM Tech Dig, pp., December 2001.
    • (2001) IEDM Tech Dig
    • Hisamoto, D.1
  • 9
    • 0036712445 scopus 로고    scopus 로고
    • High-performance logic and high-gain analog CMOS transistors formed by shadow-mask technique with a single implant step
    • September
    • T. Hook, J. Brown, M. Breitwisch, D. Hoyniak, and R. Mann, "High-performance logic and high-gain analog CMOS transistors formed by shadow-mask technique with a single implant step, " IEEE Trans Elec. Dev., vol. 49, pp. 1623-1627, September 2002.
    • (2002) IEEE Trans Elec. Dev. , vol.49 , pp. 1623-1627
    • Hook, T.1    Brown, J.2    Breitwisch, M.3    Hoyniak, D.4    Mann, R.5
  • 12
    • 0003514380 scopus 로고    scopus 로고
    • Cambridge, United Kingdom, Cambridge University Press
    • Y. Taur and T. Ning, Fundamentals of Modern VLSI Devices, Cambridge, United Kingdom, Cambridge University Press, 1998, p300.
    • (1998) Fundamentals of Modern VLSI Devices , pp. 300
    • Taur, Y.1    Ning, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.