Accelerating Critical Section Execution with asymmetric multi-core architectures

ACM SIGPLAN Notices

Volumn 44, Issue 3, 2009, Pages 253-264

  Suleman, M Aater ^a   Mutlu, Onur ^b   Qureshi, Moinuddin K ^c   Patt, Yale N ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

^c IBM RESEARCH   (United States)

Author keywords

CMP; Critical Sections; Heterogeneous Cores; Locks; Multi core; Parallel Programming

Indexed keywords

LOCKS (FASTENERS); MULTICORE PROGRAMMING; MULTIPROCESSING SYSTEMS; PARALLEL PROGRAMMING; SCALABILITY;

AVERAGE EXECUTION TIME; CRITICAL SECTIONS; HETEROGENEOUS CORES; MULTI CORE; MULTI- THREADED APPLICATIONS; MULTICORE ARCHITECTURES; ON-CHIP MULTIPROCESSOR; PERFORMANCE AND SCALABILITIES;

COMPUTER ARCHITECTURE;

EID: 67650796120     PISSN: 15232867     EISSN: None     Source Type: Journal    
DOI: 10.1145/1508284.1508274     Document Type: Conference Paper

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