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Volumn 95, Issue 2, 2009, Pages

Bulk and Interface effects on voltage linearity of ZrO2 - SiO2 multilayered metal-insulator-metal capacitors for analog mixed-signal applications

Author keywords

[No Author keywords available]

Indexed keywords

APPLIED VOLTAGES; BULK DIELECTRIC; DIELECTRIC THICKNESS; INTERFACE EFFECT; METAL-INSULATOR-METAL CAPACITORS; MIXED SIGNAL APPLICATIONS; MULTI-LAYERED; STACKING SEQUENCE; VOLTAGE COEFFICIENT OF CAPACITANCES; VOLTAGE LINEARITY;

EID: 67650763671     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.3182856     Document Type: Article
Times cited : (27)

References (14)
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    • The International Technology Roadmafor Semiconductors: Semicond. Assoc. Ind..
    • The International Technology Roadmap for Semiconductors: Semicond. Assoc. Ind., 2007.
    • (2007)
  • 5
    • 67650743167 scopus 로고
    • Proceedings of the IEEE Custom Integration Circuits Conference, (unpublished),.
    • T. Iida, M. Nakahara, S. Gotoh, and H. Akida, Proceedings of the IEEE Custom Integration Circuits Conference, 1990 (unpublished), p. 18.5.1.
    • (1990) , pp. 1851
    • Iida, T.1    Nakahara, M.2    Gotoh, S.3    Akida, H.4
  • 13
    • 34047246671 scopus 로고    scopus 로고
    • 0003-6951,. 10.1063/1.2719618
    • P. Gonon and C. Valĺe, Appl. Phys. Lett. 0003-6951 90, 142906 (2007). 10.1063/1.2719618
    • (2007) Appl. Phys. Lett. , vol.90 , pp. 142906
    • Gonon, P.1    Valĺe, C.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.