Architectural enhancements in stratix-III and stratix-IV

Proceedings of the 7th ACM SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA'09

Volumn , Issue , 2009, Pages 33-41

  Lewis, David ^a   Ahmed, Elias ^a   Cashman, David ^a   Vanderhoek, Tim ^a   Lane, Chris ^a   Lee, Andy ^a   Pan, Philip ^a  

^a ALTERA CORPORATION   (Canada)

Author keywords

Design; FPGA architecture; Memory; Power management; Static power

Indexed keywords

ARCHITECTURAL ENHANCEMENT; BENCHMARK DESIGNS; CORE AREA; EXPERIMENTAL EVALUATION; FPGA ARCHITECTURE; FPGA ARCHITECTURES; FPGA MODELING TOOLKITS; HETEROGENEOUS MEMORY; MEMORY; MEMORY ARCHITECTURE; MEMORY BLOCKS; MEMORY STRUCTURE; PERFORMANCE LOSS; POWER MANAGEMENT; PROGRAMMABLE POWER; SIMPLE MODIFICATIONS; STATIC POWER; TOTAL POWER;

ARCHITECTURE; BENCHMARKING; ELECTRIC POWER MEASUREMENT; ENERGY MANAGEMENT; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); LOGIC GATES; RANDOM ACCESS STORAGE; WIRELESS TELECOMMUNICATION SYSTEMS;

ARCHITECTURAL DESIGN;

EID: 67650650402     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1508128.1508135     Document Type: Conference Paper

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