A new redundant binary booth encoding for fast 2n-bit multiplier design

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 6, 2009, Pages 1192-1201

  He, Yajuan ^a   Chang, Chip Hong ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

Arithmetic circuit; Booth encoding algorithm; Digital multiplier; Energy delay product; Redundant binary adder (RBA)

Indexed keywords

DELAY CIRCUITS; DIGITAL ARITHMETIC; ENCODING (SYMBOLS); MULTIPLYING CIRCUITS;

ARITHMETIC CIRCUIT; BOOTH ENCODING; DIGITAL MULTIPLIER; ENERGY DELAY PRODUCT; REDUNDANT BINARY ADDERS;

SIGNAL ENCODING;

EID: 67650489076     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2008503     Document Type: Article

References (29)

1. C. Shi, W. Wang, L. Zhou, L. Gao, P. Liu, and Q. Yao, "32B RISC/DSP media processor: MediaDSP3201," SPIE Embedded Processors for Multimedia and Communications II, vol. 5683, pp. 43-52, Mar. 2005.
2. N. Slingerland and A. J. Smith, "Measuring the performance of multimedia instruction sets," IEEE Trans. Comput., vol. 51, no. 11, pp. 1317-1332, Nov. 2002.
3. L. Yang, K. Zhang, H. Liu, J. Huang, and S. Huang, "An efficient locally pipelined fft processor," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 53, no. 7, pp. 585-589, Jul. 2006.
4. H.-Y. Lee and I.-C. Park, "Balanced binary-tree decomposition for area-efficient pipelined fft processing," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 4, pp. 889-900, Apr. 2007.
5. O. T.-C. Chen, L.-H. Chen, N.-W. Lin, and C.-C. Chen, "Application-specific data path for highly efficient computation of multistandard video codecs," IEEE Trans. Circuits Syst. Video Technol., vol. 17, no. 1, pp. 26-42, Jan. 2007.
6. M. Katona, A. Pizurica, N. Teslic, V. Kovacevic, and W. Philips, "A real-time wavelet-domain video denoising implementation in FPGA," EURASIP J. Embedded Syst., pp. 1-12, 2006.
7. S. Perri, P. Corsonello, and G. Cocorullo, "A 64-bit reconfigurable adder for low power media processing," Electron. Lett., vol. 38, no. 9, pp. 397-399, Apr. 2002.
8. A. Beaumont-Smith, J. Tsimbinos, C. C. Lim, and W. Marwood, "A VLSI chip implementation of an A/D converter error table compensator," Computer Standard & Interfaces, vol. 23, pp. 111-122, 2001.
9. A. Avizienis, "Signed-digit number representations for fast parallel arithmetic," IRE Trans. Electron. Computers, vol. EC-10, pp. 389-400, Sep. 1961.
10. N. Takagi, H. Yasuura, and S. Yajima, "High-speed VLSI multiplication algorithm with a redundant binary addition tree," IEEE Trans. Comput., vol. C-34, no. 9, pp. 789-796, Sep. 1985.
11. H. Edamatsu, T. Taniguchi, T. Nishiyama, and S. Kuninobu, "A 33 MFLOPS floating point processor using redundant binary representation," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, CA, Feb. 1988, pp. 152-153.
12. B. Parhami, Computer Arithmetic Algorithms and Hardware Designs. New York: Oxford Univ. Press, 2000.
13. H. Makino, Y. Nakase, H. Suzuki, H. Morinaka, H. Shinohara, and K. Mashiko, "An 8.8-ns 54 × 54-bit multiplier with high speed redundant binary architecture," IEEE J. Solid-State Circuits, vol. 31, no. 6, pp. 773-783, Jun. 1996.
14. Y. Kim, B.-S. Song, J. Grosspietsch, and S. F. Gillig, "A carry-free 54b × 54b multiplier using equivalent bit conversion algorithm," IEEE J. Solid-State Circuits, vol. 36, no. 10, pp. 1538-1545, Oct. 2001.
15. Y. He and C. H. Chang, "A power-delay efficient hybrid carry-lookahead/carry-select based redundant binary to two's complement converter," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 2, pp. 336-346, Feb. 2008.
16. S. Kuninobu, T. Nishiyama, and T. Taniguchi, "High speed MOS multiplier and divider using redundant binary representation and their implementation in a microprocessor," IEICE Trans. Electron., vol. E76-C, no. 3, pp. 436-445, Mar. 1993.
17. S.-H. Lee, S.-J. Bae, and H.-J. Park, "A compact radix-64 54 × 54 CMOS redundant binary parallel multiplier," IEICE Trans. Electron. vol. E85-C, no. 6, pp. 1342-1350, Jun. 2002.
18. J.-Y. Kang and J.-L. Gaudiot, "A simple high-speed multiplier design," IEEE Trans. Comput., vol. 55, no. 10, pp. 1253-1258, Oct. 2006.
19. Y. He, C. H. Chang, J. Gu, and H. A. H. Fahmy, "A novel covalent redundant binary Booth encoder," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS'2005), Kobe, Japan, May 2005, vol. 1, pp. 69-72.
20. N. Besli and R. G. Deshmukh, "A novel redundant binary signed-digit (RBSD) Booth's encoding," in Proc. IEEE Southeast Conf., Columbia, SC, Apr. 2002, pp. 426-431.
21. O. L. MacSorley, "High-speed arithmetic in binary computers," IRE Proc., vol. 49, pp. 67-91, Jan. 1961.
22. G. W. Bewick, "Fast multiplication: Algorithms and implementation," Ph.D. dissertation, Stanford Univ., Stanford, CA, 1994.
23. P. Kornerup, "Digit-set conversions: Generalizations and applications," IEEE Trans. Comput., vol. 43, no. 5, pp. 622-629, May 1994.
24. T. Lynch and E. E. Swartzlander, Jr, "A spanning tree carry lookahead adder," IEEE Trans. Comput., vol. 41, no. 8, pp. 931-939, Aug. 1992.
25. V. Kantabutra, "A recursive carry-lookahead/carry-select hybrid adder," IEEE Trans. Comput., vol. 42, no. 12, pp. 1495-1499, Dec. 1993.
26. Y. Wang, C. Pai, and X. Song, "The design of hybrid carry-lookahead/ carry-select adders," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 1, pp. 16-24, Jan. 2002.
27. "TSMC 0.18 μm Process 1.8-Volt SAGE-X™ Standard Cell Library Databook," Artisan Components, Inc., 2001.
28. R. Burch, F. N. Najm, P. Yang, and T. N. Trick, "A Monte Carlo approach for power estimation," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 1, no. 1, pp. 63-71, Mar. 1993.
29. R. Gonzalez, B. M. Gordon, and M. A. Horowitz, "Supply and threshold voltage scaling for low power CMOS," IEEE J. Solid-State Circuits vol. 32, no. 8, pp. 1210-1216, Aug. 1997.