A novel covalent redundant binary booth encoder

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 69-72

  He, Yajuan ^a   Chang, Chip Hong ^a   Gu, Jiangmin ^a   Fahmy, Hossam A H ^b  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^b CAIRO UNIVERSITY   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

FAST MULTIPLIERS; HIGH RADIX; NORMAL BINARIES; PARTIAL PRODUCT; PARTIAL PRODUCT REDUCTION;

ERROR COMPENSATION; FREQUENCY MULTIPLYING CIRCUITS;

MULTIPLYING CIRCUITS;

EID: 67649086674     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464526     Document Type: Conference Paper

References (6)

1. H. Edamatsu, T. Taniguchi, T. Nishiyama, and S. Kuninobu, "A 33 MFLOPS floating point processor using redundant binary representation," in Proc. Int. Solid-State Circuits Conf., pp. 152-153, 342-343, Feb. 1988.
2. H. Makino, et al., "An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture," IEEE J. Solid- State Circuits, vol. 31, no. 6, pp. 773-783, Jun. 1996.
3. N. Besli, and R.G. Deshmukh, "A novel redundant binary signed-digit (RBSD) Booth's encoding," in Proc. IEEE Southeast Conf., pp. 427-431, Apr. 2002.
4. B. Parhami, "Generalized signed-digit number systems: A unifying framework for redundant number representations," IEEE Trans. Computers, vol. 39, pp. 89-98, Jan. 1990.
5. A. Avizienis, "Signed-digit number representations for fast parallel arithmetic," IRE Trans. Computers, Sep. 1961.
6. B. Parhami, Computer Arithmetic Algorithms and Hardware Designs. Oxford Univ. Press, New York, 2000.