A reliability-aware design methodology for networks-on-chip applications

Proceedings of the DTIS'09 - 2009 4th IEEE International Conference on Design and Technology of Integrated Systems in Nanoscale Era

Volumn , Issue , 2009, Pages 107-112

  Elmiligi, Haytham ^a   A Morgan, Ahmed ^a   Watheq El Kharashi, M ^b   Gebali, Fayez ^a  

^a UNIVERSITY OF VICTORIA   (Canada)

^b Ain Shams University   (Egypt)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION-SPECIFIC; DESIGN APPROACHES; DESIGN ISSUES; DESIGN PHASIS; GRAPH-THEORETIC; MPEG-4 VIDEO; NETWORK RELIABILITY; NETWORKS ON CHIPS; ON-CHIP INTERCONNECTION NETWORK; PROBABILISTIC MEASURES; REGULAR NETWORKS; RELIABILITY AWARE DESIGN; RELIABILITY MODEL; SYSTEM RELIABILITY; TARGET APPLICATION;

ELECTRIC NETWORK TOPOLOGY; INTEGRATED CONTROL; INTERCONNECTION NETWORKS; NANOSTRUCTURED MATERIALS; RELIABILITY;

DESIGN;

EID: 67650351996     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DTIS.2009.4938035     Document Type: Conference Paper

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