Power and delay optimization for network on chip

Proceedings of the 2005 European Conference on Circuit Theory and Design

Volumn 3, Issue , 2005, Pages 273-276

  Nickray, Mohsen ^a   Dehyadgari, Masood ^a   Afzali kusha, Ali ^a  

^a UNIVERSITY OF TEHRAN   (Iran)

Author keywords

Fat Tree Topology; Genetic Algorithm; Low Power; Network on Chip

Indexed keywords

DELAY OPTIMIZATION; FAT TREE TOPOLOGY; NETWORK ON CHIP; VERTEX MAPPING;

ELECTRIC DELAY LINES; ELECTRIC POWER UTILIZATION; GENETIC ALGORITHMS; NETWORKS (CIRCUITS); OPTIMIZATION; TREES (MATHEMATICS);

MICROPROCESSOR CHIPS;

EID: 33749016034     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECCTD.2005.1523113     Document Type: Conference Paper

References (8)

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