Integration of high-κ dielectrics and metal gate on gate-all-around si-nanowire-based architecture for high-speed nonvolatile charge-trapping memory

IEEE Electron Device Letters

Volumn 30, Issue 6, 2009, Pages 662-664

  Fu, J ^a,b   Singh, Navab ^a   Zhu, Chunxiang ^b   Lo, Guo Qiang ^a   Kwong, Dim Lee ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

Gate all around (GAA); High ; Nanowire; Nonvolatile memory; TaN Al2O3 HfO2 SiO2 Si (TAHOS)

Indexed keywords

CHARGE TRAPPING MEMORIES; GATE ELECTRODES; GATE-ALL-AROUND; GATE-ALL-AROUND (GAA); HIGH-SPEED; MEMORY DEVICE; METAL GATE; NON-VOLATILE MEMORIES; NONVOLATILE CHARGES; NONVOLATILE MEMORY; PROGRAMMING PULSE; RELIABILITY PROPERTIES; SI NANOWIRE; SONOS DEVICES; TAN/AL2O3/HFO2/SIO2/SI (TAHOS); TOP-DOWN PROCESS; TUNNEL OXIDE];

CHARGE TRAPPING; ELECTRIC WIRE; GALLIUM ALLOYS; HAFNIUM COMPOUNDS; NANOWIRES; SILICON; SILICON COMPOUNDS; SILICON OXIDES; SPEED; TANTALUM COMPOUNDS;

GATE DIELECTRICS;

EID: 67649401723     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2009.2019254     Document Type: Article

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