A Profit Evaluation System (PES) for logic cores at early design stage

Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems

Volumn 3, Issue , 2001, Pages 1491-1494

  Lu, Shyue Kung ^a,b   Lee, Bung Eng ^a,b   Wu, Cheng Wen ^a,b  

^a FU JEN CATHOLIC UNIVERSITY   (Taiwan)

^b NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILDING BLOCKES; COST MODELS; EARLY DESIGN STAGES; EMBEDDED SRAM; EVALUATION SYSTEM; FAULT COVERAGES; QUALITY LEVELS; SYSTEM-ON-A-CHIP; TEST PLAN; WAFER SIZES; YIELD MODELS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; DEFECT DENSITY; DESIGN; PROGRAMMABLE LOGIC CONTROLLERS;

PROFITABILITY;

EID: 67249099332     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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