ASIC yield estimation at early design cycle

IEEE International Test Conference (TC)

Volumn , Issue , 1996, Pages 590-594

  Kim, Vonkyoung ^a   Tegethoff, Mick ^a   Chen, Tom ^a  

^a Department of Environmental and Radiological Health Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; PARAMETER ESTIMATION; PRINTED CIRCUIT DESIGN; SEMICONDUCTOR DEVICE MODELS;

BRIDGE FAULT MODEL;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030389596     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)