How ATE planning affects LSI manufacturing cost

IEEE Design and Test of Computers

Volumn 13, Issue 4, 1996, Pages 66-73

  Nakamae, Koji ^a   Sakamoto, Homare ^a,b   Fujioka, Hiromu ^a,c  

^a OSAKA UNIVERSITY   (Japan)

^b MITSUBISHI HEAVY INDUSTRIES LTD   (Japan)

^c IEEE

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TESTING; COMPUTER AIDED MANUFACTURING; COMPUTER SIMULATION; COST EFFECTIVENESS; INTEGRATED CIRCUIT TESTING; LSI CIRCUITS;

AUTOMATIC TEST EQUIPMENT (ATE);

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0030383971     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/54.544538     Document Type: Review

References (7)

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3. C. Dislis, J. Dick, and A.P. Ambler, "Algorithms for Cost Optimised Test Strategy Selection," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1993, pp. 383-391.
4. J.E. Dayhoff and R.W. Atherton, "Financial Implications of a Detailed Analysis of Test Floor Operations," Proc. IEEE Int'l Test Conf., IEEE CS Press, 1985, pp. 23-32.
5. K. Nakamae, H. Sakamoto, and H. Fujioka, "An Analysis of the Economics of the VLSI Development Including Test Cost," IEICE Trans. Fundamentals, Vol. E77-A, No. 4, Apr. 1994, pp. 698-705.
6. S.W. Director, W. Maly, and A.J. Strojwas, VLSI Design for Manufacturing: Yield Enhancement, Kluwer Academic Publishers, Boston, 1990.
7. H.M. Wagner, Principles of Operations Research: With Applications to Managerial Decisions, Prentice Hall, Old Tappan, N.J., 1975.