Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1997, Pages 157-165

  Gagnon, Yves ^a   Savaria, Yvon ^a   Meunier, Michel ^a   Thibeault, Claude ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER ARCHITECTURE; COST EFFECTIVENESS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; MICROPROCESSOR CHIPS; REDUNDANCY;

FAULT TOLERANT CIRCUITS;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 0031336709     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFTVS.1997.628321     Document Type: Conference Paper

References (10)

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