A 65 nm CMOS 30 dBm class-E RF power amplifier with 60% PAE and 40% PAE at 16 dB back-off

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 5, 2009, Pages 1372-1379

  Apostolidou, Melina ^a   Van Der Heijden, Mark P ^a   Leenaerts, Domine M W ^a   Sonsky, Jan ^b,c   Heringa, Anco ^b,c   Volokhine, Iouri ^b,c  

^a NXP SEMICONDUCTORS   (Netherlands)

^b NXP TSMC Research Center   (Netherlands)

^c NONE

Author keywords

Cascode; Class E; CMOS power amplifier (PA); Driver stage; HV device; Power added efficiency (PAE); Self biasing technique

Indexed keywords

CASCODE; CLASS-E; CMOS POWER AMPLIFIER (PA); DRIVER STAGE; HV DEVICE; POWER-ADDED EFFICIENCY (PAE); SELF-BIASING TECHNIQUE;

CMOS INTEGRATED CIRCUITS; DC GENERATORS; POWER AMPLIFIERS;

ELECTRONIC EQUIPMENT TESTING;

EID: 66149158542     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2020680     Document Type: Conference Paper

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