Making secure processors OS- and performance-friendly

Transactions on Architecture and Code Optimization

Volumn 5, Issue 4, 2009, Pages

  Chhabra, Siddhartha ^a   Rogers, Brian ^a   Solihin, Yan ^a   Prvulovic, Milos ^b  

^a NORTH CAROLINA STATE UNIVERSITY   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Memory encryption; Memory integrity verification; Secure processor architectures; Virtualization

Indexed keywords

COMPUTER SECURITY; CRITICAL SYSTEMS; DIGITAL WORLD; INTERPROCESS COMMUNICATION; MEMORY ENCRYPTION; MEMORY INTEGRITY VERIFICATION; MERKLE TREES; MODE-BASED; MULTI-CORE SYSTEMS; PERFORMANCE ISSUES; PHYSICAL ATTACKS; QUANTITATIVE ANALYSIS; SECURE PROCESSOR ARCHITECTURES; SECURE PROCESSORS; SEED COMPOSITION; SINGLE-THREADED; UNIPROCESSOR SYSTEMS; VIRTUAL MEMORY; VIRTUALIZATION;

CHEMICAL ANALYSIS; COMPUTER ARCHITECTURE; NETWORK SECURITY; QUALITY ASSURANCE; SLITTING MACHINES;

CRYPTOGRAPHY;

EID: 66149091931     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/1498690.1498691     Document Type: Article

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