CMOS integrated stress mapping chips with 32 N-Type or P-Type piezoresistive field effect transistors

Proceedings of the IEEE International Conference on Micro Electro Mechanical Systems (MEMS)

Volumn , Issue , 2009, Pages 769-772

  Gieschke, P ^a   Nurcahyo, Y ^a   Herrmann, M ^a   Kuhl, M ^a   Ruther, P ^a   Paul, O ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG CIRCUITRY; DIE AREA; DIGITAL LOGIC; INVERSION LAYER; LINEAR RESPONSE; NOISE BEHAVIOR; NORMAL STRESS; P-TYPE; PIEZO-RESISTIVE; PIEZORESISTIVE EFFECTS; PMOS DEVICES; SENSOR CHIPS; SEPARATE DEVICES; STRESS SENSITIVITY; STRESS SENSOR; THEORETICAL PREDICTION;

MESFET DEVICES; SENSORS;

FIELD EFFECT TRANSISTORS;

EID: 65949109294     PISSN: 10846999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMSYS.2009.4805496     Document Type: Conference Paper

References (11)

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