Feasibility of ultra-low k1 lithography for 28nm CMOS node

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 7274, Issue , 2009, Pages

  Mimotogi, Shoji ^a   Takahata, Kazuhiro ^a   Murakami, Takashi ^b   Nagahara, Seiji ^b   Takeda, Kazuhiro ^b   Satake, Masaki ^a   Kitamura, Yosuke ^a   Ojima, Tomoko ^a   Fujise, Hiroharu ^a   Seino, Yuriko ^a   Ema, Tatsuhiko ^a   Yonemitsu, Hiroki ^a   Takakuwa, Manabu ^a   Nakagawa, Shinichiro ^a   Kono, Takuya ^a   Asano, Masafumi ^a   Kyoh, Suigen ^a   Harakawa, Hideaki ^a   Nomachi, Akiko ^a   Ishida, Tatsuya ^a   Hasegawa, Shunsuke ^a   Miyashita, Katsura ^a   Tominaga, Makoto ^b   Inoue, Soichi ^a   more..

^a TOSHIBA CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

28nm node; Half node; Immersion lithography; Rigorous simulation; Single exposure; Ultra high density SRAM; Ultra low k1 lithography

Indexed keywords

28NM NODE; HALF NODE; IMMERSION LITHOGRAPHY; RIGOROUS SIMULATION; SINGLE EXPOSURE; ULTRA-HIGH DENSITY SRAM; ULTRA-LOW K1 LITHOGRAPHY;

LOGIC DEVICES; MAGNETIC FIELDS; PHOTOLITHOGRAPHY; STATIC RANDOM ACCESS STORAGE;

NANOTECHNOLOGY;

EID: 65849289157     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.814040     Document Type: Conference Paper

References (5)

1. F. Uesawa et al., "Lithography of choice for the 45-nm node: new medium, new wavelength, or new beam?", SPIE Vol. 5377, 34(2004)
2. S.Mimotogi et al., "Optical Lithography Technologies for 45nm-Node CMOS", SPIE Vol.5754,196(2005)
3. [3] S.Mimotogi et al., "Performance of Immersion Lithography for 45nm-node CMOS and Ultra-High Density SRAM with 0.25um2", SPIE Vol.6520-8(2007) (Pubitemid 47551163)
4. S.Mimotogi et al., "Patterning Strategy and Performance of 1.3NA Tool for 32nm Node Lithography", SPIE Vol.6924-21(2008)
5. S.Nagahara et al., "Resist process control for 32-nm logic node and beyond with NA ≥1.30 immersion exposure tool", SPIE Vol.7273-15(2009)