Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 783-792

  Al Ars, Zaid ^a   Van de Goor, Ad J ^a   Braun, Jens ^b   Richter, Detlev ^b  

^a DELFT UNIVERSITY OF TECHNOLOGY   (Netherlands)

^b INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

Defect simulation; Embedded DRAM; Fault primitives; Memory testing; Opens; Temperature effect

Indexed keywords

COMPUTER SIMULATION; EMBEDDED SYSTEMS; FAILURE ANALYSIS; HIGH TEMPERATURE TESTING; SEMICONDUCTOR STORAGE; STRESS ANALYSIS; THERMAL EFFECTS;

MEMORY TESTING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0035684158     PISSN: 10893539     EISSN: None     Source Type: Journal    
DOI: 10.1109/TEST.2001.966700     Document Type: Article

References (10)

1. Analysis of a deceptive destructive read memory fault model and recommended testing
2. Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs
3. Overview of status and challenges of system testing on chip with embedded DRAMs
4. The behavior and testing implications of CMOS IC logic gate open circuits
5. How we test Siemens' embedded DRAM cores
6. March LA: A test for linked memory faults
7. Industrial evaluation of DRAM tests
8. Functional memory faults: A formal notation and a taxonomy
9. Tutorial: Synchronous dynamic memory test construction, a field approach