Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems

IET Computers and Digital Techniques

Volumn 3, Issue 3, 2009, Pages 235-246

  Liu, Q ^a   Constantinides, G A ^a   Masselos, K ^b   Cheung, P Y K ^a  

^a IMPERIAL COLLEGE LONDON   (United Kingdom)

^b UNIVERSITY OF PELOPONNESE   (Greece)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION CODES; ARRAY REFERENCES; BENCHMARK CIRCUITS; DATA RE USE; DESIGN CYCLES; DESIGN EXPLORATIONS; DESIGN OPTIONS; EFFICIENT DESIGNS; FPGA-BASED PLATFORMS; LOW-POWER FPGA; MULTIPLE-CHOICE KNAPSACK PROBLEMS; ON CHIPS; ON-CHIP MEMORIES; OPTIMAL DESIGNS; OPTIMISATION; POWER CONSUMPTION; POWER MODELS; POWER SAVINGS; POWER-EFFICIENT; RECONFIGURABLE SYSTEMS; SYSTEM ENERGIES;

APPLICATIONS; BENCHMARKING; DATA TRANSFER; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE CODING; INTEGER PROGRAMMING; SPACE RESEARCH;

STRUCTURAL DESIGN;

EID: 64549123962     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt.2008.0039     Document Type: Article

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