A register allocation algorithm in the presence of scalar replacement for fine-grain configurable architectures

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn I, Issue , 2005, Pages 6-11

  Baradaran, Nastaran ^a   Diniz, Pedro C ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATION THEORY; FIELD PROGRAMMABLE GATE ARRAYS; IMAGE PROCESSING; SIGNAL PROCESSING;

CODE KERNELS; EXECUTION CYCLES; REGISTER ALLOCATION ALGORITHM;

DATA STORAGE EQUIPMENT;

EID: 33646948267     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.35     Document Type: Conference Paper

References (14)

1. F. Balasa, F. Catthoor, and H. DeMan. Dataflow-driven Memory Allocation for Multi-dimensional Signal Processing systems. In Intl. Conf. on Computer Aided Design, 1994.
2. N. Baradaran, J. Park, and P. C. Diniz. Compiler Reuse Analysis for the Mapping of Data in FPGAs with RAM Blocks. In IEEE Conf. on Field-Programmable Technology, 2004.
3. P. Briggs, K. Cooper, K. Kennedy, and L. Torczon. Coloring Heuristics for Register Allocation. In ACM Conf. on Programming Language Design and Implementation, 1989.
4. D. Callahan, S. Carr, and K. Kennedy. Improving Register Allocation for Subscripted Variables. In ACM Conf. on Programming Language Design and Implementation, 1990.
5. M. Gokhale and J. Stone. Automatic Allocation of Arrays to Memories in FPGA Processors with Multiple Memory Banks. In IEEE Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, pp. 63-69, 1999.
6. S. Goldstein, H. Schmit, M. Moe, M. Budiu, S. Cadambi, R. Taylor, and R. Laufe. PipeRench: A Coprocessor for Streaming Multimedia Acceleration. In 26th Intl. Symp. on Comp. Architecture, ACM Press, pp. 28-39, 1999.
7. P. Jha and N. Dutt. High-level Library Mapping for Memories. ACM Trans. on Design Automation of Electronic Systems, 5(3):566-603, January 1999.
8. M. Kandemir and A. Choudhary. Compiler-directed Scratch Pad Memory Hierarchy Design and Management. In Design Automation Conference, 2002.
9. D. Kolson, A. Nicolau, N. Dutt, and K. Kennedy. Optimal Register Assignment to Loops for Embedded Code Generation. ACM Trans. on Design Automation of Electronic Systems, 1(2):251-279, 1996.
10. I. Ouaiss and R. Vemuri. Hierarchical Memory Mapping During Synthesis in FPGA-based Reconfigurable Computers. In Design Automation and Test in Europe, 2001.
11. B. So and M. Hall. Increasing the Applicability of Scalar Replacement. In ACM Symp. on Compiler Construction, 2004.
12. M. Weinhardt and W. Luk. Memory Access Optimization for Reconfigurable Systems. IEE Proc.-Comput. Digit. Tech., 148(3): 105-112, 2001.
13. Xilinx Inc. Virtex 2.5v FPGA Product Spec.(v2.4)), 2000.
14. XPP Technologies, Inc. The XPP White Paper., 2002.