45nm high-k/metal-gate CMOS technology for GPU/NPU applications with highest PFET performance

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 285-288

  Huang, H T ^a   Liu, Y C ^a   Hou, Y T ^a   Chen, R C J ^a   Lee, C H ^a   Chao, Y S ^a   Hsu, P F ^a   Chen, C L ^a   Guo, W H ^a   Yang, W C ^a   Perng, T H ^a   Shen, J J ^a   Yasuda, Y ^a   Goto, K ^a   Chen, C C ^a   Huang, K T ^a   Chuang, H ^a   Diaz, C H ^a   Liang, M S ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS TECHNOLOGIES;

ELECTRON DEVICES;

EID: 50249169394     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418924     Document Type: Conference Paper

References (7)

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6. Y. Yasutake et al., VLSI Tech. Symp., p.48, 2007.
7. Z. Luo et al., VLSI Tech. Symp., p.16, 2007.