A design environment for high-throughput low-power dedicated signal processing systems

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 3, 2002, Pages 420-431

  Rhett Davis, W ^a,b   Zhang, Ning ^a,c   Camera, Kevin ^a,c,d   Marković, Dejan ^a,d   Smilkstein, Tina ^a,d   Josie Ammer, M ^d   Yeo, Engling ^a,d   Augsburger, Stephanie ^a,d   Nikolić, Borivoje ^a,d   Brodersen, Robert W ^a,d  

^a IEEE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c Atheros Communications   (United States)

^d UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Application specific integrated circuits; Design automation; Design methodology; Integrated circuit design; Parallel architectures; System analysis and design

Indexed keywords

SYSTEM-LEVEL DESIGN;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DATA FLOW ANALYSIS; PARALLEL PROCESSING SYSTEMS; SIGNAL PROCESSING; SIGNAL RECEIVERS; SYSTEMS ANALYSIS; TIME DIVISION MULTIPLE ACCESS; TRANSISTORS;

INTEGRATED CIRCUIT LAYOUT;

EID: 6444245678     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.987095     Document Type: Article

References (26)

1. The network computer and its future
2. Minimizing power consumption in digital CMOS circuits
3. VLSI for OFDM
4. Architectural evaluation of flexible digital signal processing for wireless receivers
5. The role of custom design in ASIC Chips
6. A floorplan-based planning methodology for power and clock distribution in ASIC's
7. Structural and behavioral composition of VLSI
8. A case study of the FIRST silicon compiler
9. An integrated CAD system for algorithm-specific IC design
10. Silicon compiler lets system makers design their own VLSI chips
11. Automated design management using traces
12. A framework for comparing models of computation
13. Analysis and design of low-energy flip-flops
14. Design methodology for PicoRadio networks
15. VLSI architectures for iterative decoders in magnetic recording channels
16. A new architecture for the fast Viterbi algorithm
17. A 1-Gb/s, four-state, sliding block Viterbi decoder