Efficiency and scalability of barrier synchronization on NoC based many-core architectures

Embedded Systems Week 2008 - Proceedings of the 2008 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES'08

Volumn , Issue , 2008, Pages 81-89

  Villa, Oreste ^a   Palermo, Gianluca ^b   Silvano, Cristina ^b  

^a PACIFIC NORTHWEST NATIONAL LABORATORY   (United States)

^b POLITECNICO DI MILANO   (Italy)

Author keywords

Barrier; Efficiency; Manycore; Multicore; NoC; Scalability; Synchronization

Indexed keywords

COMPLEXATION; COMPUTER SOFTWARE; ELECTRIC NETWORK TOPOLOGY; INTEGRATED CIRCUITS; MESSAGE PASSING; MICROPROCESSOR CHIPS; PARALLEL ARCHITECTURES; PROGRAM COMPILERS; SCALABILITY; SYNCHRONIZATION;

BARRIER; BARRIER SYNCHRONIZATIONS; CYCLE-ACCURATE SIMULATORS; MANY-CORE ARCHITECTURES; MANYCORE; MASTER SLAVES; MICROPROCESSOR DESIGNS; MULTICORE; NETWORK TOPOLOGIES; NETWORKS ON CHIPS; NOC; PARALLEL PROCESS; SCALING BEHAVIORS; SIMPLE NETWORKS; SINGLE CHIPS; TARGET ARCHITECTURES; VARIABLE NUMBERS;

EMBEDDED SYSTEMS;

EID: 63649096141     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1450095.1450110     Document Type: Conference Paper

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