Source-line programming scheme for low voltage operation NAND flash memories

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1999, Pages 37-38

  Takeuchi, Ken ^a   Satoh, Shinji ^a   Imamiya, Kenichi ^a   Sugiura, Yoshihisa ^a   Nakamura, Hiroshi ^a   Himeno, Toshihiko ^a   Ikehashi, Tamio ^a   Kanda, Kazushige ^a   Hosono, Koji ^a   Sakui, Koji ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DATA STORAGE EQUIPMENT; ELECTRIC FIELD EFFECTS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC GATES; MICROPROCESSOR CHIPS; SILICON ON INSULATOR TECHNOLOGY; WAVEFORM ANALYSIS;

HIGH SPEED PROGRAMMING; NAND FLASH MEMORY; PROGRAM BITLINE; PROGRAM DISTURBANCE;

NAND CIRCUITS;

EID: 0033281038     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)