메뉴 건너뛰기




Volumn , Issue , 2008, Pages 1771-1774

A fully-differential subthreshold SRAM Cell with auto-compensation

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; 90NM CMOS; BIT LINES; CELL STRUCTURES; COMPENSATION MECHANISMS; FULLY DIFFERENTIALS; NOISE-INTERFERENCES; SIMULATION RESULTS; SRAM CELLS; SRAM DESIGNS; STATIC-NOISE MARGINS; STORAGE NODES; SUB THRESHOLDS; SUPPLY VOLTAGES; WRITE MARGINS;

EID: 62949209323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746384     Document Type: Conference Paper
Times cited : (11)

References (8)
  • 3
    • 34548858947 scopus 로고    scopus 로고
    • A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy
    • Feb
    • N. Verma and A. P. Chandrakasan, "A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy," ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 328-329
    • Verma, N.1    Chandrakasan, A.P.2
  • 4
    • 34548813602 scopus 로고    scopus 로고
    • A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme
    • Feb
    • T. Kim, J. Liu, J. Keane, and C. H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme," ISSCC Dig. Tech. Papers, pp. 330-331, Feb. 2007.
    • (2007) ISSCC Dig. Tech. Papers , pp. 330-331
    • Kim, T.1    Liu, J.2    Keane, J.3    Kim, C.H.4
  • 5
    • 34748830993 scopus 로고    scopus 로고
    • A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM
    • Oct
    • J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
    • (2007) IEEE J. Solid-State Circuits , vol.42 , Issue.10 , pp. 2303-2313
    • Kulkarni, J.P.1    Kim, K.2    Roy, K.3
  • 6
    • 49549103577 scopus 로고    scopus 로고
    • A32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS
    • Feb
    • I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 388-389, Feb. 2008.
    • (2008) ISSCC Dig. Tech. Papers , pp. 388-389
    • Chang, I.J.1    Kim, J.J.2    Park, S.P.3    Roy, K.4
  • 7
    • 33746369469 scopus 로고    scopus 로고
    • Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS
    • July
    • B. H. Calhoun and A. P. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, July 2006.
    • (2006) IEEE J. Solid-State Circuits , vol.41 , Issue.7 , pp. 1673-1679
    • Calhoun, B.H.1    Chandrakasan, A.P.2
  • 8
    • 16244371339 scopus 로고    scopus 로고
    • Variability in Sub-100nm SRAM Designs
    • Nov
    • R. Heald and P. Wang, "Variability in Sub-100nm SRAM Designs," Proc. IEEE/ACM ICCAD, pp. 347-352, Nov. 2004.
    • (2004) Proc. IEEE/ACM ICCAD , pp. 347-352
    • Heald, R.1    Wang, P.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.