A fully-differential subthreshold SRAM Cell with auto-compensation

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Volumn , Issue , 2008, Pages 1771-1774

  Chang, Mu Tien ^a   Hwang, Wei ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; 90NM CMOS; BIT LINES; CELL STRUCTURES; COMPENSATION MECHANISMS; FULLY DIFFERENTIALS; NOISE-INTERFERENCES; SIMULATION RESULTS; SRAM CELLS; SRAM DESIGNS; STATIC-NOISE MARGINS; STORAGE NODES; SUB THRESHOLDS; SUPPLY VOLTAGES; WRITE MARGINS;

CMOS INTEGRATED CIRCUITS; LOGIC DESIGN;

STATIC RANDOM ACCESS STORAGE;

EID: 62949209323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/APCCAS.2008.4746384     Document Type: Conference Paper

References (8)

1. A. Wang, B. H. Calhoun, and A. P. Chandrakasan, Subthreshold Design for Ultra Low-Power Systems. Springer US, 2006, ch. 1, pp. 1-6.
2. B. H. Calhoun and A. P. Chandrakasan, "A 256kb Sub-threshold SRAM in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 628-629, Feb. 2006.
3. N. Verma and A. P. Chandrakasan, "A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy," ISSCC Dig. Tech. Papers, pp. 328-329, Feb. 2007.
4. T. Kim, J. Liu, J. Keane, and C. H. Kim, "A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme," ISSCC Dig. Tech. Papers, pp. 330-331, Feb. 2007.
5. J. P. Kulkarni, K. Kim, and K. Roy, "A 160 mV Robust Schmitt Trigger Based Subthreshold SRAM," IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2303-2313, Oct. 2007.
6. I. J. Chang, J. J. Kim, S. P. Park, and K. Roy, "A32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS," ISSCC Dig. Tech. Papers, pp. 388-389, Feb. 2008.
7. B. H. Calhoun and A. P. Chandrakasan, "Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1673-1679, July 2006.
8. R. Heald and P. Wang, "Variability in Sub-100nm SRAM Designs," Proc. IEEE/ACM ICCAD, pp. 347-352, Nov. 2004.