Floorplanning for partial reconfiguration in FPGAs

Proceedings: 22nd International Conference on VLSI Design - Held Jointly with 7th International Conference on Embedded Systems

Volumn , Issue , 2009, Pages 125-130

  Banerjee, Pritha ^a   Sangtani, Megha ^b   Sur Kolay, Susmita ^a  

^a INDIAN STATISTICAL INSTITUTE   (India)

^b NVIDIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS;

FLOOR-PLANNING; FLOORPLAN; GENERATION METHODS; HETEROGENEOUS RESOURCES; NETLIST; PARTIAL RECONFIGURATIONS; RECONFIGURATION OVERHEADS; TASK INSTANCES; WIRE LENGTHS;

EMBEDDED SYSTEMS;

EID: 62949201147     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSI.Design.2009.36     Document Type: Conference Paper

References (12)

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