Heterogeneous floorplanning for FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2006, Issue , 2006, Pages 257-262

  Feng, Yan ^a   Mehta, Dinesh P ^b  

^a University of Minnesota   (United States)

^b Department of Geology and Geological Engineering   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FLOORPLANNING; HIERARCHICAL TECHNIQUES;

CONSTRAINT THEORY; HIERARCHICAL SYSTEMS; SIMULATED ANNEALING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 33748530618     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2006.96     Document Type: Conference Paper

References (7)

1. M. Wang, A. Ranjan, S. Raje, "Multi-million gate FPGA physical design challenges," in ICCAD, pp. 891-898, 2003.
2. L. Cheng, M.D.F. Wong, "Floorplan Design for Multi-Million Gate FPGAs," in ICCAD, 2004.
3. J. M. Emmert, D. Bhatia, "A methodology for fast FPGA floorplanning," in International Symposium on Field Programmable Gale Arrays, 1999.
4. Y. Feng, D. Mehta, and H. Yang, "Constrained Floorplanning using Network Flows," IEEE Transactions on Computer-Aided Design, vol. 23, pp. 572-580, Apr. 2004.
5. S.N. Adya, I.L. Markov, "Fixed-outline Floorplanning Through Better Local Search," in Proc. of ACM/IEEE International Conference Computer Design, pp. 328-334, 2001.
6. S. N. Adya and I. L. Markov, "Fixed Outline Floorplanning: Enabling Hierarchical Design," IEEE Transactions on Computer-Aided Design, vol. 11, pp. 1120-1135, Dec. 2003.
7. T.H. Cormen, C.E. Leiserson, R.L. Rivest and C. Stein, Introduction to Algorithms, Second Edition. New York: McGraw-Hill, 2001.