Floorplanning in modern FPGAs

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 893-898

  Banerjee, Pritha ^a   Sur Kolay, Susmita ^a   Bishnu, Arijit ^b  

^a INDIAN STATISTICAL INSTITUTE   (India)

^b INDIAN INSTITUTE OF TECHNOLOGY   (India)

Author keywords

Floorplanning; FPGA; Sizing; Slicing topology

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BOOLEAN FUNCTIONS; COMPUTER PROGRAMMING LANGUAGES; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS;

BENCHMARK CIRCUITS; FEASIBLE SOLUTIONS; FLOOR PLANNING; FLOOR-PLANNING; FPGA ARCHITECTURES; GENERATION METHOD; HALF-PERIMETER WIRELENGTH (HPWL); INTERNATIONAL CONFERENCES; LARGE DESIGNS; MULTIPLIER BLOCKS; PHYSICAL DESIGNS; TOPOLOGY GENERATION; VLSI DESIGNS;

EMBEDDED SYSTEMS;

EID: 48349110520     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.84     Document Type: Conference Paper

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