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Volumn , Issue , 2008, Pages 702-706

Digital subthreshold logic design - Motivation and challenges

Author keywords

Battery operated devices; Subthreshold digital circuit; Ultra lowpower

Indexed keywords

BATTERY-OPERATED DEVICES; CIRCUIT TECHNIQUES; DESIGN CHALLENGES; LEAKAGE COMPONENTS; LOW-POWER DESIGNS; LOW-POWER DISSIPATIONS; MODERN APPLICATIONS; PROPAGATION DELAYS; SIMULATION RESULTS; STRONG INVERSIONS; SUB-MICRON TECHNOLOGIES; SUBTHRESHOLD CIRCUITS; SUBTHRESHOLD DIGITAL CIRCUIT; SUBTHRESHOLD LOGIC; SUBTHRESHOLD REGIONS; SUPPLY VOLTAGES; ULTRA LOWPOWER; ULTRA-LOW POWER APPLICATIONS;

EID: 62749197610     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EEEI.2008.4736624     Document Type: Conference Paper
Times cited : (31)

References (14)
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  • 4
    • 0034867611 scopus 로고    scopus 로고
    • Scaling of Stack Effect and its Application for Leakage Reduction
    • S. Narendra, "Scaling of Stack Effect and its Application for Leakage Reduction," ISLPED '01, pp. 195-200, 2001
    • (2001) ISLPED '01 , pp. 195-200
    • Narendra, S.1
  • 5
    • 1542299283 scopus 로고    scopus 로고
    • Elements of Low Power Design for Integrated Systems
    • August
    • S. Kang, "Elements of Low Power Design for Integrated Systems," ISLPED '03, August, 2003.
    • (2003) ISLPED '03
    • Kang, S.1
  • 6
    • 33646864552 scopus 로고    scopus 로고
    • Leakage Current Mechanisms and Leakage Reduction Techniques in Deep- Submicrometer CMOS Circuits
    • Feb
    • K. Roy, S. Mukhopadhyay, H. Mahmoodi-Meimand, "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep- Submicrometer CMOS Circuits," Proceedings of the IEEE, vol. 91, no. 2, Feb. 2003
    • (2003) Proceedings of the IEEE , vol.91 , Issue.2
    • Roy, K.1    Mukhopadhyay, S.2    Mahmoodi-Meimand, H.3
  • 8
    • 11944273157 scopus 로고    scopus 로고
    • A 180 mV subthreshold FFT processor using a minimum energy design methodology
    • Jan
    • A. Wang and A. Chandrakasan, "A 180 mV subthreshold FFT processor using a minimum energy design methodology," IEEE J. Solid-State Circuits, vol. 40, pp. 310-319, Jan. 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , pp. 310-319
    • Wang, A.1    Chandrakasan, A.2
  • 9
    • 0026124101 scopus 로고
    • Current-mode subthreshold MOS circuits for analog VLSI neural systems
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    • A. G. Andreou et al., "Current-mode subthreshold MOS circuits for analog VLSI neural systems," IEEE T Neural Netw., vol. 2, pp. 205-213, Mar. 1991.
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    • Andreou, A.G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.