Digital background-calibration algorithm for "Split ADC" architecture

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 2, 2009, Pages 294-306

  McNeill, John A ^a   Coln, Michael C W ^b   Brown, D Richard ^a   Larivee, Brian J ^b  

^a Worcester Polytechnic Institute   (United States)

^b ANALOG DEVICES INC   (United States)

Author keywords

Adaptive systems; Analog digital conversion; Calibration; Digital background calibration; Mixed analog digital integrated circuits; Self calibrating

Indexed keywords

ADAPTIVE SYSTEMS; CALIBRATION; DIGITAL INTEGRATED CIRCUITS; ERRORS;

BACKGROUND CALIBRATIONS; CALIBRATION ALGORITHM; DIGITAL BACKGROUND CALIBRATION; DIGITAL CALIBRATIONS; ESTIMATION ALGORITHM; LEAST MEAN SQUARE ALGORITHMS; MIXED ANALOG-DIGITAL INTEGRATED CIRCUITS; SELF-CALIBRATING;

ANALOG TO DIGITAL CONVERSION;

EID: 61349089989     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2008.2001830     Document Type: Article

References (19)

1. J. McNeill, M. Coln, and B. Larivee, "A Split-ADC architecture for deterministic digital background calibration of a 16b 1 MS/s ADC," in Proc. ISSCC Dig. Tech. Papers, Feb. 2005, pp. 276-598.
2. J. McNeill, M. Coln, and B. Larivee, "'Split ADC' architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC," IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 2437-2445, Dec. 2005.
3. I. Galton, "Digital cancellation of D/A converter noise in pipelined A/D converters," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 3, pp. 185-196, Mar. 2000.
4. B. Murmann and B. E. Boser, "A 12b 75 MS/s pipelined ADC using open-loop residue amplification," in Proc. ISSCC Dig. Tech. Papers Feb. 2003, pp. 328-329.
5. H. Liu et al., "A 15b 20 MS/s CMOS pipelined ADC with digital background calibration," in Proc. ISSCC Dig. Tech. Papers, Feb. 2004, pp. 454-455.
6. K. Nair and R. Harjani, "A 96 dB SFDR 50 MS/s digitally enhanced CMOSpipeline A/D converter," in Proc. ISSCC Dig. Tech. Papers, Feb. 2004, pp. 456-457.
7. S. Ryu et al., "A 14b-linear capacitor self-trimming pipelined ADC," in Proc. ISSCC Dig. Tech. Papers, Feb. 2004, pp. 464-465.
8. H.-S. Lee, "A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-State Circuits, vol. 29, no. 4, pp. 509-515, Apr. 1994.
9. A. Karanicolas et al., "A 15-b 1-MSample/s digitally self-calibrated pipeline ADC,:IEEE J. Solid-State Circuits, vol. 28, no. 12, pp. 1207-1215, Dec. 1993.
10. O. E. Erdogan, P. J. Hurst, and S. H. Lewis, "A 12-b digital-background-calibrated algorithmic ADC with -90-dB THD," IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1812-1820, Dec. 1999.
11. Y. Chiu, C. W. Tsang, B. Nikolic, and P. R. Gray, "Least mean square adaptive digital background calibration of pipelined analog-to-digital converters," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 51, no. 1, pp. 38-46, Jan. 2004.
12. Y. Chiu, "A 1.8 V 14b 10 MS/s pipelined ADC in 0.18 μm CMOS with 99 dB SFDR," in Proc ISSCC Dig. Tech. Papers, Feb. 2004, pp. 458-459.
13. P. Bogner, F. Kuttner, C. Kropf, T. Hartig, M. Burian, and H, Eul, "A 14 b 100 MS/s digitally self-calibrated pipelined ADC in 0.13 μm CMOS," in Proc. ISSCC Dig. Tech. Papers Feb. 2006, pp. 832-841.
14. J. Li and U. Moon, "Background calibration techniques for multistage pipelined ADCs with digital redundancy," IEEE Trans, Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 9, pp, 531-538, Sep. 2003.
15. J. Li, G. Ahn, D. Chang, and U. Moon, "0.9 V 12 mW 2MSPS algorithmic ADC with 81 dB SFDR," in Proc. IEEE Symp. VLSI Circuits, Jun. 2004, pp. 436-439.
16. J. Li, G. Ahn, D. Chang, and U. Moon, "A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 960-969, Apr. 2005.
17. W. H. Press S. A. Teukolsky, W. T. Vetterling, and B. P. Flannery, Numerical Recipes in C: The Art of Scientific Computing. Cambridge, U.K. Cambridge Univ, Press, 1992.
18. G. Golub and C. F. van Loan, Matrix Computations, 3rd ed. Baltimore, MD: Johns Hopkins Univ. Press, 1996.
19. S. S. Haykin, Adaptive Filter Theory, 3rd ed. Upper Saddle River, NJ: Prentice-Hall, 1996.