Efficient floating-point based block LU decomposition on FPGAs

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'04

Volumn , Issue , 2004, Pages 276-279

  Govindu, Gokul ^a   Prasanna, Viktor ^a   Daga, Vikash ^b   Gangadharpalli, Sridhar ^b   Sridhar, V ^b  

^a University of Southern California ^*  (United States)

^b Satyam Computer Services Ltd India   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BANDWIDTH; COMPUTATIONAL METHODS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; ENERGY DISSIPATION; ENERGY EFFICIENCY; LINEAR ALGEBRA; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL SCIENCES COMPUTING; SIGNAL PROCESSING; THROUGHPUT; WIRELESS TELECOMMUNICATION SYSTEMS;

DOMAIN-SPECIFIC MODELING (DSM); EMBEDDED COMPUTING; ENERGY PERFORMANCE; LOW-LEVEL SIMULATIONS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 12744281744     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. Altera, http://www.altera.com/.
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3. S. Choi and V. K. Prasanna. Time and Energy Efficient Matrix Factorization using FPGAs. 13th International Conference on Field Programmable Logic and Applications (FPL 2003), September 2003.
4. T. H. Cormen, C. E. Leiserson, and R. L. Rivest. Introduction to Algorithms. 2001.
5. G. Govindu, S. Choi, V. Prasanna, V. Daga, S. Gangadharpalli, and V. Sridhar. A High-performance and Energy Efficient Architecture for Floating-point based LU Decomposition on FPGAs. In Reconfigurable Architectures Workshop, New Mexico, USA, April 2004.
6. J. Jang, S. Choi, and V. Prasanna. Area and Time Efficient Implementation of Matrix Multiplication on FPGAs. In Proc. of The First IEEE International Conference on Field Programmable Technology, California, USA, December 2002.
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8. Xilinx. http://www.xilinx.com.
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