Power-analysis attack on an ASIC AES implementation

International Conference on Information Technology: Coding Computing, ITCC

Volumn 2, Issue , 2004, Pages 546-552

  Örs, Siddika Berna ^a   Gürkaynak, Frank ^b   Oswald, Elisabeth ^c,d   Preneel, Bart ^a  

^a UNIVERSITY OF LEUVEN   (Belgium)

^b ETH ZURICH   (Switzerland)

^c GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

^d Technologiebeobachtung   (Austria)

Author keywords

AES; Power analysis attack

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; CORRELATION METHODS; INFORMATION ANALYSIS; MICROCONTROLLERS; SCHEDULING;

ADVANCED ENCRYPTION STANDARD (AES); POWER ANALYSIS ATTACK; SELECTION PROCESS; SIDE CHANNEL ATTACKS;

CRYPTOGRAPHY;

EID: 3042545023     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/itcc.2004.1286711     Document Type: Conference Paper

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